Abstract
The objective of this project is to design the critical ADC components of the radar signal processing chain in a manner that is optimized for the FM/PM CW automotive radar application. Two analog techniques―an elastic input S/H structure and a split-ADC reference pre-charging technique that obviate power-hungry ADC input drivers and reference voltage buffers, respectively, will be investigated in this SAR ADC work to achieve ultra-low power consumption for automotive RADAR applications.
Report
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